- Engineered a full virtual memory subsystem for the egos-2k+ teaching OS on a RISC-V 32-bit (RV32I) platform, implementing the Sv32 two-level page table scheme from scratch in C — gaining deep familiarity with kernel memory layout including text, data, stack, and heap regions.
- Designed and populated a radix-tree-based hierarchical page table, configuring page directory entries (PDEs) and page table entries (PTEs) with correct permission bits (R/W/X/U/V) to enforce memory protection across user and kernel address spaces.
- Built an identity-mapped region for system/kernel processes to ensure safe physical-to-virtual address continuity during early boot and privileged execution
- Implemented virtual-to-physical address translation in software, decomposing virtual addresses into VPN[1], VPN[0], and page offset fields — reinforcing hardware MMU behavior at the software level.
- Engineered context-switch support by correctly saving and restoring the satp CSR register (mode + ASID + PPN), ensuring each process operates within its own isolated address space with zero cross-process memory leakage.
- Developed a page allocator and deallocation routine to track and reclaim physical page frames, preventing memory leaks across process lifetimes.
- Diagnosed and resolved page-fault exceptions using GDB, interpreting scause trap codes to distinguish instruction, load, and store faults — developing systematic low-level debugging skills transferable to kernel and systems work.
- Demonstrated end-to-end ownership of a complex systems project: from understanding hardware specs (RISC-V ISA manual) to implementing and validating a working virtual memory system on a real OS codebase
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Pagination
RISC-V Sv32 Virtual Memory System
- C
- Operating System
- Memory
- Data Structure
- GDB
- RISC-V
- Assembly